New compact FET models under development are typically developed using preferably Verilog-A high-level programming language. But Verilog-A models are oftentime executed using slower than already fully developed and matured compact models that were previously translated into the C programming language, optimized and tightly integrated into the simulators, also known as built-in models. For instance, when comparing transient simulation or DC simulation runtimes in an HSPICE simulator between a built-in version and the Verilog-A version of a fully developed and matured PSP v102.3 compact FET model, it was found that the built-in version was executed 8 to 12 times faster.
There are some compact models, like a dedicated IDDQ (quiescent supply current) leakage model, that should ideally only be used in a DC analysis since they may be inaccurate with respect to predicting the active current and the signal timing. However, a model like the IDDQ leakage model is typically used to predict the quiescent leakage of logic circuits in various logic states. Unfortunately, circuit designers presently do not have the option to toggle all the states of sequential logic circuits which states are a function of the previous states. Thus, circuit designers are presently forced to run an IDDQ leakage model in a transient simulation. This, however, can be unreasonably time consuming, particularly for large circuits or when examining hundreds of smaller logic circuits in a standard cell library.
Present approaches to reduce simulation runtime can be divided into three categories: code restructuring, approximations and circuit/scope reduction. Code restructuring includes avoiding redundant calculations, limiting loops, limit function calls, use of macros, limit or clever use of math function, and the like. Approximations include series expansion of equations, using simpler expressions, and limit variable ranges. Circuit/scope reduction includes reducing the characterization of circuits into circuit sub-blocks and to consider only a subset of PVT (Process Voltage Temperature) corners and logic states and then extrapolate to the full circuit and complete set of PVT corners and logic states. Of these three methods, the circuit/scope reduction offers the most significant runtime improvement, but at the highest cost of loss of accuracy.
With respect to the first two approaches, regarding code restructuring and approximations, the aforementioned methods make the code less readable and more difficult to modify. Since code readability and ease of modifying the code is of significant importance during development, they cannot be efficiently and practically addressed. In addition, high-level languages like Verilog-A have limited capability for making calls to external functions that may help to optimize the execution.
A second problem requiring attention revolves around a designer wanting to accurately predict in any logic state signal regimes, such as the active current, the signal timing and the IDDQ leakage, designers may have to run one or more compact models in at least two more different simulations. For accurate prediction of the active current and signal timing, the designer can use any of existing models, such as BSIM, PSP, HiSim, EKV and the like. For IDDQ leakage, there is presently no industry standard. However, such models are likely under development due to the increasingly important contribution of the IDDQ leakage current to the total energy consumption. But even if a single compact model would be capable of accurately predicting all three current regimes, in all likelihood it would come at the expense of increased complexity and increased execution time, neither of which is an attractive trade-off.
Regardless as to whether the designer would want to use a single model to predict all three signal regimes in the logic states of a sequential circuit, the designer might still, currently, require to run two simulations, i.e., a transient simulation and an additional DC analysis, to reduce the overall runtime, because true DC conditions may require an unacceptable long transient simulation time for signal stabilization, particularly if the time constants are large.
It should be noted that from various simulator reference manuals, it would seem that it should be possible to mix various analyses and models within a single netlist through the use of the HSPICE alter command and by saving operating conditions during a transient simulation and subsequently loading the operating conditions as initial conditions in a DC analysis. However, it is not possible to do it. Firstly, once a transient analysis has been specified, e.g., at the top level, and a DC analysis is specified in the first alter command, it cannot prevent that the transient analysis be repeated following an alter command nor that the saving of the operating points is repeated. This is a significant waste of runtime if the designer only intends to run the transient analysis once and have the operating conditions saved once, and both done at the top level. Secondly, it is impossible to load initial conditions files successively in an automatic fashion in the alter command due to file extension assumptions built into the simulators. One may therefore conclude that present simulators are simply not built to enable designers to control the fine-grain execution of a multiple of analyses.
Another problem with present simulators is that each time a new model library is specified in an alter section, the simulator needs to read the models and the circuit, and then error check it. This is done even though the same libraries are loaded repeatedly in an alternating fashion, resulting in having serious consequences on the runtime for very small circuit sizes, where the read in time dominates, and for very large circuit sizes, where error checking time is preponderant.
Therefore there is a need for a method to speed up the simulation of compact models that, for example, are available only as non built-in models and compact models that are under development such as compact FET models being developed in Verilog-A.
There is a further need to enhance the circuit simulator to enable it to switch analysis types and compact MOSFET models on the fly to obtain among other things all the required information related to the three current regimes, reducing runtime to obtain the IDDQ leakage.
Moreover, there is a need to achieve the foregoing more conveniently during a single simulation and using a single netlist with simple notation.
Furthermore, there is a need to accomplish the aforementioned requirements in a fast and effective manner in order to eliminate redundant time spent on reading in and error checking models and circuits that have already been previously read in and error checked and to eliminate unnecessary repetitive rerunning of analyses.